The process of designing an IC has several stages of planning and analysis. One of the planning stages is known as the floor planning stage, which is performed by a floor planning tool. The floor planning stage generally involves placement of the larger components of the design in a top-level floor plan followed by partitioning of the remaining logic into blocks. During the partitioning process, the floor planning tool analyzes a netlist containing a list of all of the logic gates and their connectivity and groups the logic gates into blocks in a way that minimizes the routing of the electrical conductors that interconnect the blocks. As part of the block partitioning process, the blocks are placed in the top-level floor plan such that blocks that communicate with each other are in closer proximity to one another than blocks that do not communicate with one another or that communicate with one another relatively infrequently.
After the floor planning process has been performed, the floor plan is sent to a routing tool that determines the electrically-conductive routes, or nets, needed to establish the necessary connectivity. During the routing process, the routing tool attempts to place all of the routes that interconnect any two blocks within a channel that corresponds to the shortest available path between the two blocks. The shortest available path is commonly referred to as the ideal path. Each channel comprises a portion of one or more metal layers that extend between the blocks. Each channel has a limited width and thickness, i.e., limited resources. If there are insufficient resources available in a channel for all of the routes that are needed, the routing tool will attempt to place the remaining routes in a channel that corresponds to the next shortest path between the two blocks. When the routing tool uses a path other than the ideal path, this is commonly referred to as meandering.
After the routing tool has performed the routing process, the routed floor plan is returned to the floor planning tool, which performs some route quality analyses to determine whether the routes meet certain physical constraints. If they do not, then the designer uses the floor planning tool to modify the floor plan. The modified floor plan is then sent back to the routing tool, which again generates a route plan. There may be several iterations of the floor planning and routing processes before a satisfactory routed floor plan has been achieved.
Once a satisfactory routed floor plan has been achieved, the IC design process moves to a resistor capacitor (RC) extraction stage during which an RC extraction tool extracts the parasitic values of the IC design. After the RC extraction stage has been completed, the IC design process moves to a static timing analysis stage during which a static timing analysis tool analyzes the design and determines whether the design meets static timing performance criteria. In many cases, meandering-induced timing failures are detected during the static timing analysis stage, resulting in the design being returned to the floor planning stage for modification of the floor plan. After the floor plan has been modified, the design is again returned to the routing tool, which modifies the routes based on the modified floor plan. The design is then returned to the RC extraction stage followed by the static timing analysis stage.
FIGS. 1 and 2 are pictorial diagrams that demonstrate all of the aforementioned stages, the amount of time that is typically required for each stage, and the iterations that often occur between the various stages. As shown in FIG. 1, the floor planning stage typically takes about one to two days and the routing stage typically takes four to seven days. Thus, a single iteration of the floor planning and routing processes typically takes about five to nine days. As shown in FIG. 2, the RC extraction stage typically takes about two to three days and the static timing analysis stage typically takes about four to five days. Thus, a single iteration of the floor planning, routing, RC extraction, and static timing analysis processes typically takes about 11 to 15 days.
If multiple iterations of the loop shown in FIG. 1 or of the larger loop shown in FIG. 2 have to be performed, several weeks or months can be consumed to arrive at the final routed floor plan. There are typically multiple iterations of both loops before the final routed floor plan is achieved, which can result in schedule delays and missed deadlines. In addition, because die sizes are typically set before the complete analysis has been performed, resources may be over estimated or under estimated, resulting in wasted die area or unexpected die size growth, both of which lead to increased costs.
One alternative to performing all of these iterations would be to calculate the routing by hand to make sure that the design will meet static timing constraints, but this process would also be very time consuming and is prone to human error. It is known to place “bus guides” at locations in the design during the floor planning stage to define channels for certain routes. Bus guides are often used to force timing-critical buses to be routed over channels that have the most resources. Using bus guides for this purpose is advantageous, but the designer must have knowledge of where to place them and which channels have excess resources, which the designer may not always possess.
Accordingly, a need exists for a solution that reduces the number of iterations that need to be performed in order to arrive at a final routed floor plan.